Dyplo Development System for Xilinx Zynq

Dyplo simplifies and accelerates Zynq development by providing the ability to connect various processing units and distribute and control processes across the hardware/software boundary.

Dyplo is FPGA programming made software friendly, allowing out-of-the-box integration of CPU and FPGA in a Linux target environment. It affords considerable architectural freedom, and extends to run-time re-use of FPGA fabric.

Dyplo enables you to postpone architectural choices to a later stage as you can move functionality around the platform when performance issues are identified.

When combined with Miami Zynq system-on-modules, Dyplo offers software engineers a highly abstracted environment under which to harness the potential of FPGA acceleration.

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DyploBeeldbeursgroot_aangepastcpu_fpga1500x1481One of the complexities of Zynq is the combination of hardware- (FPGA) and software- (CPU) functionality. In order to program your Zynq product optimally, you need an infrastructure to join the FPGA and CPU. Dyplo offers this completely.

From an engineering perspective to make your total integrated Zynq solution work as intended, the key enabler is a good and solid infrastructure. Software and hardware engineers are both experts in their specific domain. Integration is not the main focus of either hardware or software. In order to ensure the best and fastest results, Dyplo provides a standard out-of-the-box infrastructure. This enables all engineers to focus on what they do best.

Adding IP blocks to your Dyplo infrastructure is simple. As long as the code is AXI compliant, hassle free integration is guaranteed.

The amount of data increases day by day.

The internal structures of the FPGAs are extremely suitable for data processing in terms of available processing power, low energy consumption and memory bandwidth.

But on the downside, programming FPGAs is complex, and they have typically fixed functionality once programmed.

Dyplo gives the FPGA this flexibility, totally controlled and managed.

The next step in data acceleration is enabled by Dyplo giving the FPGA the flexibility to process large data sets with low energy consumption.

Partial reconfiguration means that you can re-use, start, stop or copy parts of the cores of your FPGA dynamically when required. For many years, utilization of this specific area of FPGAs has been out of reach for many FPGA users. Dyplo gives you an easy way to benefit from partial reconfiguration. From a user perspective, simply earmarking blocks for acceleration allows the Dyplo system to accelerate your application as and when it is required. Imagine, reducing the size of your fabric by 60% while only using 40% of that fabric simultaneously!

The Zynq version of Dyplo is based on Linux. In future Dyplo will be ported to many operating systems – please ask for further details.
    florida-kit-brightThe Dyplo development kit is a combination of your choice of Miami SoM module and Florida Carrier Board complete with Dyplo-on-board, touch screen, reference designs (audio, video and medical), individual case and full set of cables. As well as a generic development kit, specific kits are available for Medical, and for PCIe-based development.

    The Kit comes with a complete and maintained Linux BSP, downloadable via GitHub, including OpenEmbedded and BitBake supported build environment. Dyplo, the operating system extension for FPGA and CPU integration, is provided with the kit.

    The development kit offers a complete system, including display, communication interface and specific data interface.

    Please contact us for further details.

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    The Zynq competence level of your teams increase drastically. When “talking Dyplo”, integration issues are taken care of, and a common language can be used across the whole CPU and FPGA platform. This new way of working means:

    Cost savings:
    •BOM savings: proven 20% by tested use case.
    ◦In general significant BOM reduction due to re-use of FPGA fabric
    ◦Zynq integration related cost savings

    •Development time savings: proven 30% by tested use case
    ◦Out-of-the box integration of CPU & FPGA
    ◦FPGA programming accessible for software developers
    ◦Shorter time to market

    •Power reduction by using FPGA technology
    •FPGA size reduction by re-using parts of your FPGA

    From a system perspective

    Suspend architectural choices to a much later stage as you can move functionality across platform when bottle-necks arise.

    From a hardware perspective

    Your field of expertise will be valued more, and used more frequently by enabling software engineers to access parts of your domain in a controlled and managed manner. You can focus on your expertise, while full integration of your state of the art work is enabled by the Dyplo Framework.

    From a software perspective

    Programming an FPGA is totally different compared to a CPU. Dyplo extends the FPGA domain to your software domain. The infrastructure is ready to use, and the processor blocks are designed and can be managed in such a way as if you were using software processors, but then much, much more powerful.

    Typically, FPGA’s have a fixed behavior once programmed. Dyplo offers an ease way to reprogram parts of your FPGA resources, runtime if you like!

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