Boundary scan test solutions from Corelis, and timing diagram analysis
and ASIC verification productivity tools from Forte Design Systems (Chronology).
Select one of the products listed below to visit the product pages.
Cynapps and Chronology merge to deliver tools for ASIC verification.
Corelis is a world leader in the field of IEEE-1149.1 boundary-scan
JTAG testing, JTAG In-System Programming of Flash memories & CPLDs,
JTAG emulation and debugging, and microprocessor development tools.
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