Impulse - Design Acceleration

Accelerate your embedded software applications!

1. Automated C to hardware compilation

CoDeveloper's advanced hardware compilation technology is capable of extracting parallelism from standard C statements, including blocks of statements that span multiple C source file lines or entire loop bodies. There is no need to insert explicit statements or keywords (such as "par" statements) in order to exploit parallelism within your C applications. Instead, the CoDeveloper compiler analyzes the statements in your C language description, optimizes those statements and, when possible, combines multiple statements into a single instruction stage representing one clock cycle. You can express control over this process (for example by specifying blocks of statements that are to be pipelined, or loops that are to be unrolled) but in general it is not necessary to understand or describe statement-by-statement parallelism in your Impulse C applications in order to generate parallel hardware.

The hardware compilation features of CoDeveloper include:

• Common compiler optimizations such as common sub-expression elimination, constant folding and dead code elimination
• Automatic parallelizing of multiple, sequential C statements into equivalent instruction stages
• User-controllable instruction stage pipelining (a pipeline pragma)
• User-controllable instruction stage delays (a stagedelay pragma)
• User-controllable loop unrolling (the unroll pragma)
• Automatic generation of synthesizable RTL from C processes
• Automatic generation of hardware-to-hardware and hardware-to-software interfaces, including dual-clock interfaces

2. Support for a multi-process programming model

While compiler optimizations and automated parallelism extraction are important, equally important is giving the programmer control over coarse-grained, system-level parallelism. This is provided in Impulse C through the following library features:

• Processes, allowing multiple, parallel units of computation to be described and interconnected
• Streams, which provide an efficient, self-synchronizing method of data movement between parallel processes
• Shared memories (and associated block read and block write functions), which provide an alternate method of data communication useful for static or randomly accessed data
• Signals, which provide a means of synchronizing processes to specific events or conditions
• Registers, which provide a direct, unbuffered means of passing data into and out of hardware processes.
• A configuration function that allows a complete Impulse C application consisting of multiple parallel processes to be created, and allows the necessary inter-process communication channels (typically streams, signals and/or shared memories) to be described.

These parallel programming features of Impulse C provide a programming model and a desktop verification methodology allowing system-level parallelism to be explicitly defined by the programmer, while lower level parallelism (the inner code loops and compute-intensive operations that represent actual algorithms) are automatically exploited by the Impulse CoDeveloper compiler.

Get started fast

CoDeveloper includes extensive documentation and sample projects that help you get started fast. Platform-specific, step-by-step tutorials show you how to create multi-process, highly parallel applications entirely in C language and compile them to mixed hardware/software platforms such as the FPGA development board shown below.

Single-board FPGA development kits are excellent platforms for application development and hardware/software prototyping. (Altera NiosT development kit featuring StratixT FPGA. Photo courtesy of Altera Corporation.)

Get ready for extreme performance

If you're looking for extreme performance from your embedded applications, FPGAs are the way to get it. And whether you're using a single FPGA with an embedded processor or an array of dozens of FPGAs (as shown below), Impulse C gives you the power to quickly create massively parallel applications that take FPGA-based computing to the next level, without the need to write low-level HDL code.

Extreme performance: a 27-node Xilinx Virtex-II FPGA-based supercomputing platform programmed in part using Impulse C (photo courtesy of Montana State University).

There is no catch. If you can write C for applications targeting standard processors, then you can write C for programmable hardware. To be sure, there are some new concepts to learn, and there are some new constraints placed on the C code that you will write for the hardware portions of your application. But you'll be happy to learn that you don't need to be a hardware or FPGA expert to dramatically accelerate your applications.

Does Impulse C require an embedded microprocessor?

Although Impulse C is designed with embedded processors in mind (it can, for example, automatically generate the necessary processor to FPGA interfaces), it is not actually necessary to use an embedded processor in order to make use of Impulse C. Instead, you may choose to use Impulse C for describing and compiling specific processes that will be interfaced (using traditional hardware design tools and methods) with other IP components within one or more FPGAs. In this usage, Impulse C and the CoDeveloper compiler may be thought of as a module generator.

Does Impulse C replace existing hardware description languages?

Impulse C is not intended to replace HDLs for general purpose logic design. Instead, Impulse C is most useful for quickly moving algorithms expressed in C language to an FPGA for algorithm acceleration. Impulse C applications (which may consist of just one hardware process, or many processes connected to form a parallel system) therefore have well-defined communication interfaces (including streams, signals and simple registers) allowing them to communicate with external hardware and software components.

Indeed, for the highest possible application performance you should plan to use Impulse C and the CoDeveloper tools to get more quickly to an application prototype, then apply your existing HDL expertise to further accelerate and optimize key algorithms and processes. The benefit of using Impulse C is that it gives you more opportunities to experiment with alternative algorithmic approaches, a faster path to a working prototype and greater opportunities to improve system-level performance through iterative design methods.

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