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Impulse CoDeveloper C to VHDL for FPGAImpulse - Design Analysis


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bulletFPGA CoDesign
bulletANSI C to RTL
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bulletOptimal Applications
bulletFrequently Asked Questions...

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Find and fix communication bottlenecks, fast!

Debugging highly parallel hardware/software applications introduces special challenges. During desktop simulation, CoDeveloper's unique Application Monitor makes it possible to observe your application as it runs (whether under the control of a debugger or when running as a native development host application) and view outputs and other information collected as a result of instrumenting your code. Application monitoring is an effective way to see where potential data bottlenecks are occurring, to identify possible deadlock conditions and to zero in on problems your application may have with data movement, process synchronization and load balancing.

The Application Monitor lets you to observe the application's processes and buffered data flowing through the system.
The Application Monitor lets you to observe the application's processes and buffered data flowing through the system.

By adding Impulse C instrumentation functions to your application, you can more easily make sense of how your application operates and quickly find errors. In a typical monitoring scenario, each process in the application creates one or more monitor log windows that are used to display formatted or unformatted text messages. In addition, the Application Monitor displays a graphical view of the state of buffered data streams, making it easy for you to identify and improve potential data bottlenecks.

Log windows for each running process help instrument and debug highly parallel applications.
Log windows for each running process help instrument and debug highly parallel applications.

For applications consisting of large numbers of processes, and in particular applications that include arrays of processes (such as heavily pipelined or systolic array applications), the Application Monitor can provide visibility during debugging that would otherwise be impractical or impossible. And by observing when (and under what conditions) your data buffers become full and your processes are blocked you can make better design decisions with the goal of optimizing overall application performance.

Log windows can represent each instance of a process being replicated in a pipelined array.
Log windows can represent each instance of a process being replicated in a pipelined array.

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CoDeveloper provides C to RTL design and compilation for various FPGA platforms including Xilinx and Altera. It enables you to create your own FPGA-based custom platform and to target systems with external processors, including DSPs.
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Online Documentation at our Literature Centre...See our Literature Centre for documents and other associated files for this product group.

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