Impulse CoDeveloper - Frequently Asked Questions

Select from the questions below to view the answer you require:

1. Does this product fully support my selected FPGA?
2. Does CoDeveloper require that an embedded processor be used in the FPGA?
3. Does Impulse C allow me to compile my legacy C applications to hardware?
4. Is Impulse C appropriate for DSP applications?
5. Can Impulse C applications be simulated before compiling to hardware?
6. Can I combine my own HDL with Impulse C?
7. Does CoDeveloper support Verilog output?
8. Can I call external hardware components (or hard macros) from within an Impulse C process?
9. Can CoDeveloper handle "untimed" C?
10. Can CoDeveloper pipeline loops?
11. Can CoDeveloper unroll loops?
12. Can CoDeveloper perform partial unrolling?
13. Is floating point math supported?
14. Is fixed point math supported?
15. How does Impulse C compare to hand-crafted HDL code?
16. How do I optimize a C design to improve performance and utilization?
17. How does Impulse C relate to System C?
18. Can Impulse C be used for FPGA-based grid computing?
19. Is CoDeveloper compatible with UML tools?
20. Why are Impulse products so inexpensive compared to other C-to-hardware tools?

1. Q: Does this product fully support my selected FPGA?

CoDeveloper generates synthesizable HDL outputs that are compatible with most common FPGA device families. For users of Altera and Xilinx devices the tool includes specific optimizations and makes use of FPGA-specific library elements to increase performance and support certain types of hardware interfaces (such as Xilinx FSL and OPB, or Altera's Avalon).

2. Q: Does CoDeveloper require that an embedded processor be used in the FPGA?

No, an embedded processor is not required. If the target device includes a Xilinx MicroBlaze or PowerPC processor core, or an Altera Nios or Nios II processor, then the CoDeveloper compiler allows hardware processes to be described in C and connected to software running on the embedded processor. If, however, the goal is to connect Impulse C generated processes to other hardware elements (such as those written in VHDL or Verilog) then there is no need to use an embedded processor, and CoDeveloper can be thought of as a hardware IP block generator.

3. Q: Does Impulse C allow me to compile my legacy C applications to hardware?

Impulse C is a set of library functions that support parallel programming using data streams, signals and shared memories. The CoDeveloper compiler tools are capable of accepting one or more C files containing such programs (multiple C subroutines connected via streams, signals and memories) and generating equivalent low-level hardware. As such, Impulse C and CoDeveloper are not specifically intended for taking large C applications that are written using traditional C programming techniques (function calls, etc.) and compiling these applications to equivalent hardware. Such applications are best-suited to processor architectures, but may be accelerated dramatically by identifying key subroutines and inner code loops and moving them to hardware. This is the primary purpose of Impulse C and the CoDeveloper compiler tools. Using Impulse C, key subroutines can be partitioned (using data streaming, for example) and moved into dedicated hardware with relatively little effort. This can be done in an iterative manner, with software-based simulations being performed along with actual generation of prototype hardware to simplify debugging and system-level optimization.

4. Q. Is Impulse C appropriate for DSP applications?

Yes, Impulse C is being used today for a variety of DSP-related applications. The streaming programming model is idea for such applications, and the support for fixed-width integers simplifies the creation of many types of DSP filters. Future releases of the Impulse C libraries and CoDeveloper compiler will include more DSP-specific features, including support for fixed-point math libraries.

5. Q: Can Impulse C applications be simulated before compiling to hardware?

Yes, Impulse C includes a simulation library compatible with standard ANSI C. This means that your applications (which may include multiple parallel processes written in C and communicating via streams, signals and shared memories) can be compiled in standard C development environments including Visual Studio and GCC/GDB. When executed in these environments, parallel behavior is emulated using multiple threads of execution which may be observed using a combination and standard debugging techniques and the Impulse Application Monitor.

6. Q: Can I combine my own HDL with Impulse C?

Yes, you can make use of your own VHDL or Verilog as part of the design flow by merging design files at the time of synthesis or at the time of place-and-route. CoDeveloper generates synthesizable VHDL (not low-level or obfuscated netlists) so you can use CoDeveloper as a VHDL module generator alongside more traditional methods of design. The Impulse C process interface (data streams and signals) is easy to understand for the purpose of integration with other modules written in VHDL. CoDeveloper Universal includes extended documentation and examples demonstrating how to connect Impulse C processes (written in C and compiled to VHDL) to external VHDL modules via the stream I/O interface. Sample VHDL test benches and tutorials help you get started.

7. Q: Does CoDeveloper support Verilog output?

CoDeveloper currently generates only VHDL outputs. Verilog output is planned for a future release. (Note that all popular FPGA synthesis tools accept either VHDL or Verilog, so the use of VHDL as an intermediate synthesis format is not generally an issue.)

8. Q: Can I call external hardware components (or hard macros) from within an Impulse C process?

Calling hardware macros from within an Impulse C process is not currently supported. A future release of CoDeveloper will include the ability to specify external components from within an Impulse C process. This will be useful for creating custom hardware functions (which are typically expressed as a single statement in C) optimized for specific applications.

9. Q: Can CoDeveloper handle "untimed" C?

"Untimed" refers to the lack of clock stage boundaries (or "par" statements) being specified in the C code. CoDeveloper supports the automated parallelizing of C code, without the need to express such parallelism at the level of individual statements or blocks of code. To do this, CoDeveloper's Stage Master optimizer analyzes your C code, finds interdependencies and collapses multiple C statements into single instruction stages representing a single clock cycle. This automated creation of parallel hardware can be controlled by the programmer (for size/speed tradeoffs) using a compiler pragma.

10. Q: Can CoDeveloper pipeline loops?

Yes, CoDeveloper does support pipelining of loops. Loop pipelining is enabled for a given loop using a PIPELINE pragma. Examples supplied with CoDeveloper describe how to enable and control pipelining. Note that loop pipelining introduces additional hardware (for pipeline control) and should therefore be used carefully.

11. Q: Can CoDeveloper unroll loops?

Yes, CoDeveloper supports the automatic unrolling of loops using the UNROLL compiler pragma. Loop unrolling can dramatically increase the performance of many types of algorithms, but can also result in large increases in the size of generated hardware.

12. Q: Can CoDeveloper perform partial unrolling?

Partial unrolling of loops is not currently supported, but is planned for a later release. The STAGEDELAY pragma can be used to help balance size and speed tradeoffs for many types of structures, including unrolled loops.

13. Q: Is floating point math supported?

CoDeveloper does not support floating point types in hardware processes, but interfaces to third-party floating point libraries are planned for a future release. Floating point operations in FPGAs require a substantial amount of FPGA resources so it is often better to create integer or fixed point equivalents when possible.

14. Q: Is fixed point math supported?

Impulse C includes fixed width integer data types which can be used to implement basic fixed-point operations, but does not include support for a complete fixed-point math library (which must include such things as saturation and rounding modes, etc.). Fixed point math features are being considered for a future release.

15. Q. How does Impulse C compare to hand-crafted HDL code?

Just as assembly code programs are generally more compact than the equivalent code written in C, so is hand-crafted VHDL generally tighter than VHDL automatically derived from C. However, as a general rule the lower the level of abstraction (the form of the program), the longer it takes to write and the more costly it is to maintain. Furthermore, as the size of applications grows, the less practical it is to perform a complete manual optimization. This suggests that as design sizes grow, the practical result is that compiler-generated HDL outputs will begin to approach hand-written HDL in terms of size efficiencies and performance, assuming that the time available for hand-optimization of the hardware is finite. For smaller designs, the major advantage of Impulse C is dramatically shorter time to a working prototype, not design efficiency. CoDeveloper does, however, include extensive documentation

16. Q. How do I optimize a C design to improve performance and utilization?

By using appropriate C coding styles and through an understanding of the compiler tools it is possible to optimize for both performance and for utilization. (Note that this is true when programming for traditional microprocessors and DSPs as well as for FPGAs.)

The first priority of the CoDeveloper compiler is for performance, as measured in required clock cycles to complete a given task. A related, secondary priority is to reduce gate delays, which directly impact maximum clock rates. Because optimizing for speed can result in very large amounts of logic being generated, Impulse C allows certain optimizations (such as loop unrolling and pipelining) to be controlled via language-level pragmas. In a typical usage, Impulse C users are first concerned with getting a working prototype, which may operate at reduced rates but is sufficient to verify correct functionality (in simulation and in hardware) and to analyze dataflow at a system level. Later optimizations may include using modified C coding styles, specifying certain optimizer controls or re-partitioning the application to better take advantage of system-level parallelism and "tune" the application and its constituent algorithms to the target platform (FPGA device and/or embedded controllers). With nominal effort (e.g. days) Impulse C users have shown acceleration results of 100 to 300x through some relatively simple techniques, while at the same time reducing overall design size. If the performance of a given application is of paramount importance, then extra time should be budgeted for this optimization phase. If the smallest possible design size is a critical requirement, then the Impulse C user (perhaps working with an experience FPGA designer) should be prepared to replace certain portions of the generated hardware with hand-crafted HDL, using the generated HDL as an overall specification and functional benchmark.

17. Q. How does Impulse C relate to System C?

SystemC is a publicly-available, free to use library that a numer of EDA vendors have embraced at various levels. These vendors include Forte, Celoxica, Synopsys and others. SystemC is slowly gaining momentum among higher-end ASIC designers for system modeleling but at this writing has little or no traction (in fact no real awareness) among rank and file embedded systems designers. These embedded systems designers and programmers overwhelmingly choose standard ANSI C for their design activities.

Impulse has positioned itself as a provider of embedded software/hardware development tools and is not in the traditional EDA or ASIC design tools business. Impulse has therefore chosen not to make use of SystemC as a key part of its strategy. The Company will, however, provide cosimulation capabilities with SystemC in a future product release.

18. Q. Can Impulse C be used for FPGA-based grid computing?

Yes. By combining one or more traditional processors (running one or more Impulse C processes) with FPGA processing nodes (also programmed using Impulse C) it is possible to create extremely high performance computing grids using a streaming programming model. Streaming may be accomplished using high-speed serial links that map directly to Impulse C stream interfaces. There are multiple research teams using Impulse C for this purpose today. In some cases these teams are making use of hand-crafted VHDL for critical processes and using the Impulse C programming model (and automatic generation of stream interfaces) as a system-level framework, in addition to making use of the C-to-hardware compilation features of CoDeveloper. Impulse C is highly applicable to such applications.

19. Q. Is CoDeveloper compatible with UML tools?

The Impulse C programming model (which is optimized for hardware applications) emphasizes the use of data streams for data movement between related processes. There may be equivalent methods in UML for creating and using data streams (dataflow programming model) that would map well to Impulse C, however general-purpose C code emitted by UML tools is probably not appropriate for use with Impulse C. It is quite possible, however, that some subset of UML's dataflow representation could map well to Impulse C streams, and it is also possible that the C code within a specific processing module could be compatible with the Impulse C compiler. This is an area of interest to Impulse for future research.

20. Q: Why are Impulse products so inexpensive compared to other C-to-hardware tools?

Impulse was conceived of as a provider of embedded software development tools, not as an EDA company. Embedded software development tools are generally lower cost (and serve a broader market) than tools of equivalent complexity offered to electronic systems developers, and to ASIC designers in particular. We believe that other C-to-hardware tool vendors have been formed (and funded) to serve the more narrow, higher-priced EDA markets of systems-on-chip and advanced ASIC design. Their business models demand much higher revenues per user to attain rapid short-term growth in the highly competitive EDA market segment. Our vision is longer-term; we believe that Impulse C is well positioned as a tool for mainstream embedded systems programmers seeking higher performance through FPGA co-processing.

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