Select an FPGA target and compile your applications!
To implement your application on a selected programmable hardware platform,
you identify specific Impulse C processes to be compiled, select a platform
target and let CoDeveloper do the rest.
Code generation options are used to tailor the CoDeveloper output
to a specific target platform.
CoDeveloper analyzes each process to be compiled, finds opportunities for
low-level parallelism to be exploited, performs instruction scheduling,
loop unrolling and pipelining and generates hardware descriptions ready
for processing using standard hardware synthesis tools. The output
is optimized for specific device families, and interface logic is generated
allowing software processes to communicate with hardware processes via buffered
data streams, signals and via shared memory as appropriate.
The generated HDL code is compatible with widely available hardware
synthesis and simulation tools.
Once you've created, simulated and compiled your application to
create a hardware description, the final step is to implement it on
the actual programmable hardware platform. This is done using the
standard tools supplied by your programmable platform vendor. For example,
the Altera Quartus software may be used to synthesize, optimize and route
the VHDL generated by CoDeveloper for Altera platforms as shown below:
Interface libraries provided with CoDeveloper make it easy to
connect your Impulse C hardware processes with Impulse C software processes (targeting
embedded processors) in support of mixed hardware/software solutions.
CoDeveloper provides C to RTL design and compilation for
various FPGA platforms including Xilinx and Altera. It enables
you to create your own FPGA-based custom platform and to target
systems with external processors, including DSPs.
CoDeveloper provides C to RTL design and compilation for
various FPGA platforms including Xilinx and Altera. It enables
you to create your own FPGA-based custom platform and to target
systems with external processors, including DSPs.
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