Applying Boundary-Scan for Product Development

Recent marketing drive for reduced product size, such as portable phones and digital cameras, higher functional integration, faster clock rates, shorter product life-cycle with dramatically faster time to market, has created new technology trends. These new technology trends include increased device complexity, fine pitch components such as SMTs, MCMs, and BGAs, increased IC-pin count, and smaller PCB traces. This has created the following problems in product development:

Many boards include components that are assembled on both sides of the board. Most of the through-holes and traces are buried and inaccessible.

Loss of Physical Access to fine pitch components such as SMTs and BGAs makes it difficult to probe the pins and distinguish between manufacturing and design problems.

A prototype assembly is usually done by a small prototype assembly shop, in rush, with lower quality control as compared to a production house. A prototype generally will include more assembly defects than a production unit.

When the prototype arrives, a test fixture for the In-Circuit- Tester (ICT) is not available and therefore manufacturing defects can not be easily detected and isolated.

Small-size products do not have test points which makes it difficult or impossible to probe suspected nodes.

Many Complex Programmable Logic Devices (CPLDs) and Flash devices (in BGA packages) are not socketed and are soldered directly to the board.

Every time an engineer selects a new processor or a different flash device, he has to learn from scratch how to program the Flash memory

When a design includes CPLDs from different vendors, the engineer must use different in-circuit programmers to program the CPLDs.

Boundary-scan technology is the only cost effective solution that can deal with the above problems. In the last few years, the number of devices that include boundary-scan has grown exponentially. Almost every new microprocessor that is being introduced includes boundary-scan circuitry for testing and in-circuit emulation. Most of the CPLDs and FPGAs manufacturers such as Altera, Lattice, and Xilinx, to mention a few, have incorporated boundary-scan logic into their components including additional circuitry that uses the boundary-scan 4-wire interface to program their devices in-system.

As the acceptance of boundary-scan as the main technology for interconnect testing and in-circuit programming has increased, the various boundary-scan test and in-system programming tools have matured as well. The increased number of boundary-scan components and mature boundary-scan tools, as well as other factors that will be described later, provide engineers with the following benefits:

Easy to implement Design For Testability (DFT) Rules. A list of basic DFT rules is provided later in this article.

Testability report prior to PCB layout enhances DFT.

Find packaging problems prior to PCB layout.

Little need for test points.

No need for test fixtures.

More control over the test process.

Quickly diagnose (with high resolution) interconnect problems without writing any functional test code.

Program code in flash devices.

Put design configuration data into CPLDs.

JTAG emulation and source-level debugging.