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CAS-1000 I2C Bus analyser,
Exerciser, and Programmer Instrument
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Features
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Software
The major functions of this instrument include:
Monitor: Passively listens and records all target bus traffic to display state and timing records and store in files. Includes message filtering, symbolic translation, and event trigger. Bus signal and protocol conformance is continually evaluated with deviations flagged. The monitor window is shown below.
Emulator: Enables concurrent virtual devices programmed to interact with the bus in addition to those of the target. These can include a Master (capable of multi-master arbitration), and up to 32 slaves. The above monitor includes and tags this emulated traffic.
Tester: Interprets a script program file to control a go-no-go test sequence, including bus electrical/timing parametric measurements. This enables automatic target bus specification compliance and functionality validation. It is suitable for design/development as well as factory acceptance testing. The test script window is shown below.

CAS-1000
Test Script Window
Debugger: A user interactive bus I/O access portal. This enables individual bus transfers for immediate target communications. Looping supports repeated I/O patterns to facilitate external signal observations. Besides generic writing and reading of data blocks, a growing library of known standard devices is included showing interactive screens tailored to the device’s organization (such as ADCs, DACs, flash memories, SMbus behavior, etc.). The debugger window is shown below.

CAS-1000
Debugger Window
Programmer: Provides easy-to use high-speed in-system programming of I2C compatible serial EEPROMs. Two programmer windows are shown below.

CAS-1000 Programmer Window

CAS-1000 Programmer Read Device Contents Window
One application of the CAS-1000-I2C is to rapidly validate compliance of a target bus with the specification. This is supported at the electrical, timing, as well as the signaling level. Another application is to passively monitor any I/O activity transpiring on a target bus. This includes the detection of errant protocol. All such logged information is time stamped for history reconstruction. A third application is the programmed interchange of messages with the target bus system, also recorded by the monitoring function. This method can serve to generally exercise the target bus. It also supports target code development with debug stand-ins for non-existent bus devices. Finally, a general user PC to I2C communications link provides quick and direct visibility/control of target devices. This is extended to user applications via the provided API.
I2C Parameters Scope
Using the Parameters Scope tool, the CAS-1000-I2C can be utilized to quickly measure and return the basic electrical and I2C timing parameters of the target bus without setting up the advanced scripting functions of the Test tool. It can gather master specific and slave-specific parameters, such as signal timing characteristics, and also system-wide parameters, such as bus voltage, pull-up resistance, and capacitance. Each measurement is compared to maximum and minimum values loaded from a specification file and the resulting pass or fail status is shown with the measurement. The Parameters Scope provides the additional ability to display a graph of captured signal edge transition data and a trigger can be set to capture a particular I2C bus signal's rising or falling edge.

CAS-1000 Parameters Scope Window
One application of the CAS-1000-I2C is to rapidly validate compliance of a target bus with the specification. This is supported at the electrical, timing, as well as the signalling level. Another application is to passively monitor any I/O activity transpiring on a target bus. This includes the detection of errant protocol. All such logged information is time stamped for history reconstruction. A third application is the programmed interchange of messages with the target bus system, also recorded by the monitoring function. This method can serve to generally exercise the target bus. It also supports target code development with debug stand-ins for non-existent bus devices. Finally, a general user PC to I2C communications link provides quick and direct visibility/control of target devices. This is extended to user applications via the provided API.
SMBus Support
The System Management Bus, or SMBus, was defined by Intel® Corporation in 1995 and is based on the I2C bus architecture. It is used in personal computers and servers for low-speed system management communications.
SMBus is a two-wire interface through which simple system and power management related chips can communicate with the rest of the system. A system using SMBus as a control bus for these system and power management related tasks passes messages to and from devices by addressed transfers, enabling moderate transfer rates using minimal board resources. With System Management Bus, for example, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. The SMBus may share the same host device and physical bus with standard I2C components. Intel originally conceived the SMBus as the communication bus to accommodate Smart Batteries and other system and power management components.
The CAS-1000 software features SMBus decoding for common SMBus devices. Ordinarily, the raw data of the I2C transactions between SMBus devices must be manually decoded into meaningful information. With the SMBus decoding feature, a specific device address can be associated with a text file containing decoding information which allows the I2C Exerciser software to do the interpretation automatically.
The CAS-1000 also supports SMBus PEC (Packet Error Checking) message generation

CAS-1000 Bus Monitor Window in SMBus Decoding Mode
Hardware
At the core of the CAS-1000-I2C is an on-board engine whose logic performs the low level interaction with the bus. This element receives set-up, direction and drive data from the host via a USB 2.0 port. Conversely, as bus activity is detected and characterised, its transitional information is conveyed up to the host for further processing.
The PC host operates this processor via the USB 2.0 port under the provided Windows application. Alternatively, the user may create custom software which calls included API C/C++ library routines to easily operate the I2C I/O, avoiding hardware management details.
In addition there is an array of onboard physical interface elements to facilitate the required measurement, capture, and operating capabilities. This includes a number of DACs to develop the various programmable voltages.
High-speed A2D converters enable the capture of I2C bus waveforms for analysis, including sensing adjustable thresholds (with hysteresis), signal level crossing detection, and transition time determination.
Programmable Clock Rate
The CAS-1000-I2C clock rate is programmable under software for use when emulating a master. It is capable of supporting standard mode, fast mode and high-speed mode transfers up to 5 Mbits/sec as well as intermediate values. For emulated slaves, clocking comes from the target, whose rate is automatically accommodated up to 5 MHz since the clock rate automatically tracks the target bus master.
Test Discrete I/O Signals
Two programmable lines can be operated under PC host software control. They are available to stimulate the target system or sense target conditions in coordination with the testing. Each line is programmable as input, output TTL, or output open-drain. One of these outputs can be a dedicated trigger and programmably linked to the SMB output trigger connector. This supports test synchronization with external laboratory equipment. The other discrete I/O can be tied to the other SMB as an input trigger.
Adjustable Voltage Levels
The signal level of the set of discrete I/O and trigger lines is programmable from 1.25 to 3.3V in increments of less than 5 mV. The I2C bus reference voltage can be programmed as target driven through its bus pull-ups or driven from the CAS-1000-I2C. This target reference voltage can also be measured. When the CAS-1000-I2C is programmed to source this reference level (both SCL and SDA signals), the voltage can be set with less than 5 mV resolution over the range of 0.8 to 5V. In such cases, the target pull-ups should be removed. For the case that the CAS-1000-I2C reference voltage does drive the bus, one of a set of pull-up resistors (the same value for both bus signals) can be selected. The resistor values span the range from 250 to 50K ohms. In such cases, the target pull-ups should also be removed. Additionally, sensed bus signal high and low individual threshold levels can be adjusted. This supports the bus hysteresis requirements. Default software-determined values are available.
Auxiliary TAP Port
The CAS-1000-I2C includes an IEEE-1149.1 JTAG Test Access Port (TAP). This port can be used to perform boundary-scan testing and in-system programming of flash, EEPROMs and PLDs on the target system and is both hardware and software compatible with the complete ScanPlus and ScanExpress family of IEEE-1149.1 test and in-system programming products offered by Corelis. This feature is mutually exclusive to the I2C functionality and requires it to be put into the TAP mode.
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