Corelis - Boundary Scan Solutions : Testability Evaluation  

In order to develop test vectors and evaluate the testability of a customer's design we must have the following information:

1. Netlist

We can accept almost any netlist format as long as we know what the format is so that we can convert it to the required Telesis format. Note that Orcad schematics capture can generate Telesis directly. This netlist should match the netlist of the actual board and so therefore MUST be fully back annotated with the correct U/IC numbers and pin numbers. Generally the best way to achieve this to export a netlist from the PCB layout system rather than the schematic editor.

2. Scan chain

List the boundary scan devices to reflect their order in the chain along with the BSDL file name:

• U1 "XC5206_PQ208.bsd"
• U35 "XCV400_BG352.bsd"
• U29 "10K100_TQ144.bsd"
• 3. BSDL files

BSDL files are typically found on the relevant chip manufacturer web sites. If you are having a difficulty getting the files please let us know and we will search our archives to see if we can get it for you.

4. Schematics

Must be in Acrobat (.pdf) format or OrCAD format. We can also use hard copy printout.

5. Bill of Materials

Not mandatory - must be either a text file or a MS-Word or MS-Excel compatible file.