Boundary-scan technology is the only cost effective solution that can
deal with the prototype design problems. In the last few years, the number
of devices that include boundary-scan has grown exponentially. Almost
every new microprocessor that is being introduced includes boundary-scan
circuitry for testing and in-circuit emulation. Most of the CPLDs and
FPGAs manufacturers such as Altera, Lattice, and Xilinx, to mention a
few, have incorporated boundary-scan logic into their components including
additional circuitry that uses the boundary-scan 4-wire interface to program
their devices in-system.
Easy to implement Design For Testability (DFT) Rules. A list of basic
DFT rules is provided later in this article.
Testability report prior to PCB layout enhances DFT.
Find packaging problems prior to PCB layout.
Little need for test points.
No need for test fixtures.
More control over the test process.
Quickly diagnose (with high resolution) interconnect problems without
writing any functional test code.
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