Test Program Generation, Boundary-Scan, ScanExpressTPG

The Corelis Test Program Generator is the next generation automatic boundary-scan test pattern generation tool that takes the process of boundary-scan automation to a new level of performance and ease of use.

The ScanExpressTPG Intelligent Test Pattern Generator is the next generation automatic boundary-scan test pattern generation tool that takes the process of boundary-scan automation to a new level of performance and ease of use. ScanExpressTPG automatically generates test patterns that facilitate the pin-level fault detection and isolation of all boundary-scan testable nets on a printed circuit board (PCB). ScanExpressTPG also creates test vectors to detect faults on the pins of non-scannable components such as clusters and memories that are surrounded by scannable devices. ScanExpressTPG accepts most industry recognized CAE/CAD netlists.

ScanExpress Main Window

ScanExpressTPG provides an integrated development environment (IDE) system in which the user can generate boundary-scan tests from scratch, invoke the ScanPlusDFT Analyzer to produce test coverage reports, and invoke ScanPlus Runner to execute created tests, all from a single Graphical User Interface (GUI). The user starts with the basic board design files, adds supplemental information, generates test vectors, creates test coverage reports, and executes the tests by using the descriptive icons located on the shortcuts bar.

By utilizing ScanExpressTPG, both experienced and novice users can create boundary-scan test vectors in a fraction of the time it takes to develop these test vectors using legacy test pattern generators. Test development time is greatly reduced by automating and integrating many of the tasks that the user previously had to perform manually.

ScanExpressTPG greatly reduces the number of keystrokes and mouse clicks and eliminates text editing wherever possible. By maximizing the automation behind the complete process, boundary-scan test procedures can be developed with the least amount of time and effort while ensuring that the final test procedure is of the highest possible quality. For complete information on ScanPlusDFT Analyzer, please refer to the detailed data sheet for this product.

Automatic Detection of the JTAG Scan Chain

Test Coverage Analysis

ScanPlusDFT Analyzer calculates the test coverage of boards and systems that include a mix of boundary-scan and non-boundary-scan devices. It also helps design and test engineers to increase fault coverage and reduce boundary-scan test program development time. The figure to the right depicts a ScanPlusDFT Analyzer screen.

ScanPlusDFT Analyzer intelligently merges various testability reports generated by ScanExpressTPG and provides summary and detailed test coverage reports for the board. The combined test coverage reports help engineers to maximize the use of boundary-scan and reduce the need for "nails" access to nets and pins of the board under test.

ScanPlusDFT Analyzer is generally used after schematic capture and before PCB layout. At this stage of product development, ScanPlusDFT Analyzer can create a comprehensive test coverage reports that identifies all of the boundary-scan nets and pins and classifies them as completely tested, partially tested, or not tested. The report also recommends where to add test points (pads) for physical "nails" access if additional test coverage is required. For complete information on ScanPlusDFT Analyzer, please refer to the detailed data sheet for this product.

Test Coverage Summary Report