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Interactive modelling of timing relationships
Many people miss out on the value of this function, because they think
it's something to do with simulation, and they already have a timing simulator.
So let's start by stating that it's nothing to do with timing simulation.
You use timing diagram analysis right at the start of the design, before
you've even drawn a schematic.
 Let's
say you're doing a system design with an embedded microprocessor, or for
that matter an ASIC design which has to interface to a microprocessor
or memory.
Before you can fix the design, you have to think about the interface
and how it is specified. After scratching your head for a few moments,
you open the manufacturers' databooks so that you can see the interface
parameters, and then begin sketching waveforms on a sheet of paper.
What you immediately find is that a piece of paper is not the ideal
analysis tool when every edge has a min and max value. Whatif analysis
is also not a trivial matter with a pencil and rubber.
Chronology TimingDesigner automates this process, and does a whole lot
more. Timing parameters on a spreadsheet are automatically linked to an
interactive diagram. You can play "what-if" not just with clock speeds,
but with device speed grades as well.
Edges can be linked, not just with min/max values, but with expressions
in VHDL or Verilog, and timing constraints can be automatically monitored
by the tool.
 TimingDesigner
What's New in Version 9.0 
TimingDesigner
Frequently Asked Questions
You
can download an evaluation
version of TimingDesigner
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