EMA TimingDesigner - TimingDesigner FAQs

Select from the questions below to view the answer you require:

1. What platforms does TimingDesigner support?
2. What types of licensing arrangements are available for TimingDesigner?
3. What Import and Export formats does TimingDesigner support?
4. What other software does TimingDesigner interface with?
5. Is using the new Project Manager a requirement, even for relatively simple analysis?
6. Can I display filename or title information on a timing diagram?
7. Can I draw analog signals with TimingDesigner?
8. Does TimingDesigner support command line operation?
9. Does TimingDesigner support batch mode operation?
10. Can files written with a later version of TimingDesigner be read by an earlier version?
11. Can I introduce jitter into my Clock or Derived Clock?
12. How do I model a Phase-Locked Loop output?
13. Can I display my decoded State Machine state values?
14. How can I identify the license I am using when submitting a request for TimingDesigner Technical Support?

1. What platforms does TimingDesigner support?

For detailed system requirement visit our user area.

2. What types of licensing arrangements are available for TimingDesigner?

TimingDesigner is offered with several licensing options including perpetual and time-based. A single node locked license for PC applications is available using a hardware key; floating licenses are also available for network applications. TimingDesigner uses the FLEXlm licensing mechanism from the Globetrotter Software Division of Macrovision® Corporation for its licensing schemes, and options are available for use across LANs and WANs. TimingDesigner is not offered with a node-locked license on anything other than a hardware key configuration (PC only).

3. What Import and Export formats does TimingDesigner support?

Importing
TimingDesigner imports waveform data from the following formats:

• TimingDesigner native Timing Diagram (TD)
• Value Change Dump (VCD)
• Wave Log Format (WLF)
• Timing Diagram Markup Language (TDML) -- see note below
• Fast Signal Database (FSDB)
• User-defined format – available toolkits allow creation of a C++ or Perl files to import unique waveform formats

For timing parameter data:

• Comma Separated Value Format (CSV)
• Standard Delay Format (SDF)
• Xilinx XML-based timing report (TWX)
• Altera timing reports (TAO, RPT, and ALT) -- ALT files are TAO files with expanded timing path information

For timing library data:

• Xilinx XML-based timing report (TWX)
• Allegro post-route timing files (TXT)
• Comma Separated Value Format (CSV)

For component data:

• Electronic Design Interchange Format r2.0 netlist files (EDIF)

Exporting
TimingDesigner can export waveform data to the following formats:

• TimingDesigner native Timing Diagram (TD)
• Timing Diagram Markup Language (TDML) -- see note below

For graphic image files of waveform, parameter, and library data:

• Enhanced MetaFile Format (EMF) -- Windows only
• FrameMaker Interchange Format (MIF)
• Encapsulated Postscript (EPS)
• Tagged Image File Format (TIF)
• Joint Photographic Experts Group format (JPEG)
• Graphic Interchange Format (GIF)
• Portable Network Graphics format (PNG)
• Scaled Vector Graphics format (SVG)

For parameter and library data:

• Comma Separated Value Format (CSV)

These formats allow use of TimingDesigner diagrams with several desktop publishing tools including Adobe® FrameMaker®, Adobe® PageMaker®, and Microsoft® Word.

Note: TimingDesigner includes full import/export support for the TDML (Timing Diagram Markup Language) v1.1 standard from Si2. The TDML standard, while still in existence, has not been supported for updates and enhancements. Therefore, files from the latest versions of TimingDesigner could contain objects that may not be supported in the TDML specification. A detailed list of TDML supported objects can be found in TimingDesigner's online help system..

4. What other software does TimingDesigner interface with?

• Tau® from Mentor Graphics®
  Mentor Graphics' Tau symbolic timing analysis tool can use TimingDesigner as an entry method for building its timing models. Contact Mentor Graphics support for assistance.
  
  
• Xilinx® ISE FPGA Development Systems
  TimingDesigner provides a design flow interface to Xilinx's ISE FPGA development software. It allows designers to create ISE PAR constraints that reference timing measurements in TimingDesigner, allows importation of post PAR results from ISE for waveform timing update, and allows automatic library file creation from ISE's SpeedPrint utility.
  
  
• Altera® Quartus II® FPGA Development System
  TimingDesigner provides a design flow interface to Altera's Quartus II development software. It allows designers to create QSF PAR constraints that reference timing measurements in TimingDesigner, and allows importation of post PAR results from Quartus II for waveform timing update.
  
  
• Cadence® Tools
  TimingDesigner provides a design flow interface to Cadence's Allegro® PCB layout tools that allow creation of post PAR PCB trace delay information for waveform timing update. Also supported is EDIF 2.0 netlist import for automatic population of components in TimingDesigner's Manager window.
  
  
• Others
  Finally, because TimingDesigner stores its models in easily readable and parseable ASCII text format, it is relatively simple to write programs to interface TimingDesigner to other EDA tools, and many companies have done just that.
  
  

5. Is using the Project Manager a requirement, even for relatively simple analysis?

While its use is not required, the Manager Window does provide a more structured approach to your timing analysis requirement and is highly recommended. It offers the capability of project organization by arrangement of multiple timing diagrams by their associated component. This can greatly benefit complex project timing analysis by offering port list and netlist connectivity information that can be used for automatically merging interface protocol timing diagrams. Merged interface diagrams offer a view of protocol operation that takes into account all signal characteristics that combine to achieve an acceptable timing margin for critical timing paths.

TimingDesigner can continue to operate on a diagram-only basis, just as it has in previous releases. Simply minimize the Project Window and work exclusively in the Diagram, Parameter, and Library Windows. TimingDesigner can be configured to exit on the closure of either the Diagram Window or Manager Window (the default).

6. Can I display filename or title information on a timing diagram?

For better documentation and printing, you may wish to add additional comments (including the diagram name) to the timing diagram. This is accomplished using dynamic text substitution features in combination with provided header and footer capability.

7. Can I draw analog signals with TimingDesigner?

TimingDesigner is a timing diagram tool for modeling, analyzing, and documenting digital circuits. It does not support analog waveform analysis.

8. Does TimingDesigner support command line operation?

TimingDesigner provides many command line switches that allow non-GUI related operations, including automated analysis and execution of Tcl based batch scripts. Repetitive tasks such as changing fonts and line styles of several diagrams to conform to a documentation standard are best accomplished from a command line script.

9. Does TimingDesigner support batch mode operation?

TimingDesigner allows execution of Tcl based batch files from either the GUI interface or from a command line switch. Batch mode allows a limited subset of TimingDesigner commands to export diagrams and spreadsheets, add and edit waveforms, change diagram settings, and modify spreadsheet values.

10. Can files written with a later version of TimingDesigner be read by an earlier version?

Generally, no. TimingDesigner files are forward compatible, meaning any TimingDesigner file can always be read by the latest release. While there are some instances of earlier TimingDesigner releases reading a file generated by a later release, it is generally discouraged as there can be loss of information when doing so. Therefore, you should not rely on TimingDesigner to read files written by a newer version. In addition, some versions of TimingDesigner will not attempt to read a file written in a newer file format.

11. Can I introduce jitter into my Clock or Derived Clock?

Jitter is introduced and controlled via the Timing Relationship area of the Attributes dialog boxes for Clocks and Derived Clocks. For a clock, simply enter the amount of jitter in the Rising Jitter and Falling Jitter fields of the Clock Attributes dialog box. For a derived clock, enter the jitter amount in the Delay to Rising and Delay to Falling fields of the Derived Clock Attributes dialog box.

For complex uncertainties such as jitter compounded with signal delay, create a Variable in the Parameter Spreadsheet that has a formula specified as a function of jitter AND delay. Then enter the variable in the respective field box for appropriate jitter application.

12. How do I model a Phase-Locked Loop output?

Phase-Locked Loops (PLLs) typically generate clock outputs that are phase-shifted or that multiply the input clock frequency, and can be modeled using Derived Clocks. To model PLLs, create a Clock that represents the input clock to the PLL device. Then create a Derived Clock to model the PLL output, entering a value between 0 and 1 in the Divisor field to represent the inverse of the multiplier number. For instance, for a 4x clock, enter "0.250" in the Divisor field. Select the base clock that serves as the input. Uncertainties that are characteristic of the modeled PLL are introduced by using the Delay to Rising and Delay to Falling fields.

Derived Clocks that multiply their base clock frequency will not propagate any base clock uncertainties to their outputs. This is because PLLs typically don't inherit any characteristics from their base clock, but instead introduce their own uncertainty characteristics.

13. Can I display my decoded State Machine state values?

Decoded values are added to signals, buses, and derived signals by defining a table of encoded values and their decoded equivalents via the Decode Value button in the waveform's Attributes dialog box. With the Appearance section of the dialog box set to display the Decoded Value, the decoded equivalent for the waveforms value will be displayed when that listed value is found in the table. For example, the Verilog value of 4'b0101 on a bus may represent a read operation, so the value "4'b0101" is the encoded value and "read" is the decoded value.

14. How can I identify the license I am using when submitting a request for TimingDesigner Technical Support?

The license is identified from the Help | License Info menu command. The resulting License Information dialog box includes information that Technical Support can use to identify your license. The dialog box also includes a Save button that will save the information to a text file. This is handy if your preferred method of contacting Technical Support is via email.