TimingDesigner 6.5 supports Xilinx interface design

New release targets critical timing

With the release of TimingDesigner 6.5, Chronology continues its focus on the analysis of critical signal relationships in high speed interfacing.

Teaming up with Xilinx to add ISE import/export, Chronology have made TimingDesigner a key element in managing the timing challenges inherent in high speed FPGA design. Interface definitions can be seamlessly exchanged with ISE for timing-driven place and route, and TimingDesginer libraries of Xilinx devices can be created automatically from the switching characteristics report generated with the SpeedPrint utility within ISE.

TimingDesigner 6.5 now offers two different methods for importing SDF data, including waveform and variables.

Other highlights include dynamic reporting text, linked to the timing analysis results; parameter window row colourisation, the ability to use measure values of edge connections in formulae, and simplified entry of min/max values.

All registered users entitled to the update should have received download details by email by the end of March 2004.

For further information about the update, see our TimingDesigner "What's New" page.