timingdesigner supports SDC timing constraints

TimingDesigner version 9.1 has been released by EMA, adding support for SDC which provides the ability to interface with FPGA and ASIC design flows. By providing users the ability to generate SDC from a timing diagram, TimingDesigner is enabling design teams to move forward with confidence knowing their constraints will be representative of their original design intent, thus aiding achievement of timing closure.

TimingDesigner is the industry standard tool for interface timing design. It provides an easy to use and intuitive method for defining and analyzing interface timing requirements. The introduction of version 9.1 makes TimingDesigner the only tool that can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route.

Generating SDC directly from a timing diagram removes any confusion as to the intent behind the constraints and allows users to visually debug and refine their SDC with ease. It also greatly reduces the learning curve for users new to the SDC format.

The initial release of TimingDesigner with SDC support focuses on the Altera FPGA design flow. TimingDesigner 9.1 also includes a number of general productivity enhancements and updates.

TimingDesigner 9.1 will be available at the end of October 2008, and is free to existing customers with a valid maintenance contract. For more information, visit our TimingDesigner pages.