TimingDesigner supports Altera

Chronology has expanded the popular TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows. TimingDesigner version 8.0 is available immediately and also includes new timing diagram functions aimed to increase productivity, along with new usability enhancements tailored for datasheet creation and revision.

Tighter Integration with Vendor-Specific Design Flows
Chronology has teamed up with Altera to increase accuracy and expedite the FPGA design process by allowing users to better manage the timing challenges inherent with high-speed design. Chronology's TimingDesigner now works closely with Altera's Quartus II, providing a smooth hand-off of critical timing data between high-density FPGAs and board-level designs, so users can identify and resolve timing issues and validate that timing constraints have been met. The new features include:

Hand-off of timing analysis results are used as constraints to drive Quartus II place and route to increase timing accuracy.

Post-route timing information from Quartus II is imported by TimingDesigner, allowing validation and visual confirmation of critical internal FPGA signal timing relationships.

"Altera's Quartus II software enables the fastest path to design completion for high-density FPGA design," said Jim Smith, Altera's Director of EDA Relations. "By enabling users to quickly identify and address timing closure issues between FPGAs and other board-level components, the new integration with Quartus II and TimingDesigner will allow Altera customers to achieve even greater productivity."

TimingDesigner 8.0 also provides enhanced interfaces for board-level designers using Cadence Design System Inc.'s OrCAD Capture and Allegro PCB design tools. Users can import EDIF files from OrCAD Capture to automate the creation of design components and ports for new projects within TimingDesigner, resulting in substantial time savings. In addition, TimingDesigner 8.0 offers a seamless way to import net propagation delay information from Allegro PCB design tools, allowing users to increase the accuracy of their post-route net delay analysis results and identify unexpected timing closure issues.

Expanded Timing Diagram Functionality and New Usability Features
TimingDesigner 8.0 brings a number of new timing diagram functions and usability features to increase productivity and streamline high-speed data interface design.

Designs with high-speed data interfaces typically include multiple representations of differentially-ended signals. With TimingDesigner 8.0, users can save significant design time by simply selecting a button to designate any signal, derived signal, clock, or derived clock as a differential signal for any given diagram. TimingDesigner 8.0 also offers new Clock Enable and Output Enable equations for derived signals, simplifying the creation of selectively clocked functions and tri-state buffer representations.

In TimingDesigner 8.0, Chronology also introduces several new usability features tailored for datasheet creation and revision. It has a unique capability to provide visual context for Cause and Effect Events, where users can define a relationship between source and target edges with a curved arrow of selected line width and color. Additionally, a new Active Break feature lets users collapse time periods at selected locations within a diagram while compensating all measurements if break events are crossed. The new Nominal Value support allows designers to perform analysis with nominal or average values in addition to existing min/max values, enhancing options for datasheet creation and maintenance.