TimingDesigner 7.0 timing diagram tool

Latest version of market-leading timing diagram tool

We are now shipping TimingDesigner 7.0, the latest version of the popular interactive timing analysis and diagram product. This next generation release of TimingDesigner brings focus to the project management challenges of designing complex timing interfaces.

More stringent specifications for high speed designs means that timing analysis must now incorporate signal integrity and physical effects, as well as manage and monitor timing margins through the design process. Chronology's TimingDesigner allows users to model their timing challenges via timing diagrams and spreadsheet technology, and analyze a range of conditions to obtain accurate timing results. Designers can define timing constraints, evaluate timing parameters, create specifications, and analyze complex interfaces within their design.

Today, timing margin information changes frequently throughout the course of a design project - too often it is miscommunicated among engineering teams because it is manually extracted from documents or reports. TimingDesigner 7.0 new project manager simplifies the exchange of critical timing information and enables users to better manage the specification and analysis of high performance interfaces for their digital IC and board designs. To handle growing design complexity, designers now have the option to logically organize multiple diagram components within one project. Components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams. Designers can also merge two diagrams from different components - automatically creating an interface that accounts for component connectivity as well as managing signal duplication and propagation delays.

A number of other enhancements are included in this release. Designers can now localize library management for specific diagrams and their associated paths, avoiding time-consuming network access to large library repositories. Additionally, to simplify analysis and save debug time, designers can now designate the use of only minimum or maximum values for their diagrams (as opposed to both minimum and maximum values) to perform best-case and worst-case timing analysis. Other enhancements include waveform dividers to visually group signals together, font modifiers to better support documentation style guides, display of decoded values on valid edges of signals, derived signals, and buses, and new built-in spreadsheet functions for improved analysis reporting.

TimingDesigner 7.0 is available now. Existing users with a valid support contract should have received this update by the end of October 2004.

For further information see our TimingDesigner pages.