High Performance 2040-Pin Chip Tester

Specifically tailored for custom ASIC Boundary-Scan Validation

Corelis have recently unveiled a new high performance JTAG boundary-scan test system that allows boundary-scan testing and verification of large-scale ASIC and other high-density integrated circuits. With up to 2,040 independent test points, the ScanPlus Chip Tester provides abundant test point coverage for even the highest density BGA packages. Its ability to verify the tested device's compliance to the IEEE-1149.1 specification, and the accuracy of the BSDL file description against the actual silicon provides chip integrators with an invaluable tool when debugging silicon. The ScanPlus Chip Tester was specifically developed for today's most demanding applications including Multi-Chip-Modules (MCM) and system-on-chip (SOC) designs.

It is an intelligent boundary-scan tester that is used in conjunction with the PCI-1149.1/Turbo boundary-scan controller. Utilizing this high-speed controller, the ScanPlus Chip Tester achieves TCK speeds up to 80 MHz. The ScanPlus Chip Tester also offers excellent flexibility due to its four banks of adjustable voltage levels, separate power regulation of tester and target, four analog test channels, three programmable clock generators and on-board memory. Boundary-scan test vectors developed with Corelis' ScanPlusTPG Test Program Generator can be executed directly on the ScanPlus Chip Tester.

Until now, very expensive semiconductor testers and test fixtures were used to perform device testing and boundary-scan verification functions. The ScanPlus Chip Tester performs many of these same functions at a fraction of the cost.